This invention relates to a semiconductor non-volatile memory device composed of semiconductors.
Recently the degree of integration of semiconductor memory device has drastically increased, and along with the increase in the degree of integration, its application fields are expanding. In this trend, a semiconductor non-volatile memory that can be electrically rewritten has been applied only in limited fields including replacement with DIP switches, etc., and data memories of small capacity because of its low degree of integration.
The following is a description of an MNOS type semiconductor non-volatile memory that is well known among the semiconductor non-volatile memories.
A MNOS transistor comprises, as an insulation film beneath the gate, a very thin oxide layer with a thickness of about 20 angstroms disposed at the semiconductor substrate side, and a silicon nitride layer (Si.sub.3 N.sub.4) of several hundred angstroms disposed on its surface, and by applying a high electric field between the gate and the portion immediately beneath the gate, holes or electrons are accumulated in the trap in the silicon nitride layer by the tunnel current, and the threshold voltage of the MNOS transistor is varied, thereby storing the information.
A conventional example of a semiconductor non-volatile memory using such MNOS transistor is explained while referring to FIG. 13, which is a sectional view of a memory cell block of an N type MNOS semiconductor non-volatile memory of the one-transistor, tri-gate type (e.g.--see Japanese Patent Publication No. Sho 57-29861).
In FIG. 13, an N.sup.+ diffusion source line 2 (source region) and an N.sup.+ diffusion drain 3 (drain region) are formed in a P type silicon substrate 1. On the surface of the silicon substrate 1 adjacent to the diffusion source line 2 and diffusion drain 3, oxide layers 4, 4 are formed, and a separation gate 5 and a selection gate 6 are formed on the surface of the oxide layers 4, 4 respectively. On the surfaces of the separation gate 5 and selection gate 6, and on the surface of the silicon substrate 1 between these gates 5, 6, a very thin oxide layer 7 of about 20 angstroms in thickness is formed. Furthermore, on the surface of this very thin oxide layer 7, a silicon nitride layer (Si.sub.3 N.sub.4) 8 of about several hundred angstroms in thickness is formed. On the surface of the silicon nitride layer 8, an MNOS gate 9 is formed. The entire surface of the silicon substrate 1 is covered with an insulation film 10, and on its surface, a patterned aluminum bit line 11 is formed. Part of the bit line 11 penetrates through the insulation film 10, and contacts the diffusion drain 3.
In the construction in FIG. 13, it is the portion of the MNOS gate 9 that is responsible for storing information, and the separation gate 5, in the write disabled stated, prevents the high voltage supplied to the diffusion drain 3 from flowing into the diffusion source line 2 regardless of the gate state of the MNOS gate 9 and the selection gate 6.
However, in such a conventional semiconductor non-volatile memory, there is only one MNOS gate 9, that is, only one information memory device in one memory cell block. Accordingly, for one information memory device, two gates not storing information, that is, the selection gate 6 and separation gate 5 are needed, and it was extremely difficult to raise the degree of integration of the semiconductor chips from the viewpoint of integration of information.